Vibe Coding DiscoverTraceWeave
View on GitHubOpen-source, evidence-driven MCP server for RTL simulation debugging: correlate VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM source, hierarchy, and connectivity to trace failures to root cause.
An MCP server that helps AI assistants debug RTL simulations by correlating VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM source, hierarchy, and connectivity. Provides evidence-backed failure analysis, waveform comparison, handshake checks, and signal tracing.
Use Cases
Investigate failed or hanging RTL simulationsCompare waveforms across simulation runsTrace X/Z values to possible sourcesCheck interface handshakes and transaction completionBrowse design hierarchy and signal connectivityFind constant connections and unconnected inputs
Built With
- Language
- Python
- Frameworks
- Model Context Protocol · pyslang
Tags
RTL debugging · MCP server · hardware verification · SystemVerilog · UVM · waveform analysis · VCD · FSDB · root-cause analysis · simulation logs · signal tracing · EDA